1 From 3293689b1e19b9e607f2f7f2c6d71434e1324148 Mon Sep 17 00:00:00 2001
    2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
    3 Date: Wed, 2 Dec 2020 18:20:25 +0100
    4 Subject: [PATCH 2/7] PCI: pci-bridge-emul: Add definitions for missing
    5  capabilities registers
    6 MIME-Version: 1.0
    7 Content-Type: text/plain; charset=UTF-8
    8 Content-Transfer-Encoding: 8bit
    9 
   10 pci-bridge-emul driver already allocates buffer for capabilities up to the
   11 PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
   12 registers. Add these missing definitions.
   13 
   14 Signed-off-by: Pali Rohár <pali@kernel.org>
   15 Signed-off-by: Marek Behún <kabel@kernel.org>
   16 Cc: stable@vger.kernel.org
   17 ---
   18  drivers/pci/pci-bridge-emul.c | 39 +++++++++++++++++++++++++++++++++++
   19  1 file changed, 39 insertions(+)
   20 
   21 diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
   22 index a4af1a533d71..aa3320e3c469 100644
   23 --- a/drivers/pci/pci-bridge-emul.c
   24 +++ b/drivers/pci/pci-bridge-emul.c
   25 @@ -251,6 +251,45 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
   26                 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
   27                 .w1c = PCI_EXP_RTSTA_PME,
   28         },
   29 +
   30 +       [PCI_EXP_DEVCAP2 / 4] = {
   31 +               /* Device capabilities 2 register has reserved bits [30:27]. */
   32 +               .ro = BIT(31) | GENMASK(26, 0),
   33 +       },
   34 +
   35 +       [PCI_EXP_DEVCTL2 / 4] = {
   36 +               /*
   37 +                * Device control 2 register is RW.
   38 +                *
   39 +                * Device status 2 register is reserved.
   40 +                */
   41 +               .rw = GENMASK(15, 0),
   42 +       },
   43 +
   44 +       [PCI_EXP_LNKCAP2 / 4] = {
   45 +               /* Link capabilities 2 register has reserved bits [30:25] and 0. */
   46 +               .ro = BIT(31) | GENMASK(24, 1),
   47 +       },
   48 +
   49 +       [PCI_EXP_LNKCTL2 / 4] = {
   50 +               /*
   51 +                * Link control 2 register is RW.
   52 +                *
   53 +                * Link status 2 register has bits 5, 15 W1C;
   54 +                * bits 10, 11 reserved and others are RO.
   55 +                */
   56 +               .rw = GENMASK(15, 0),
   57 +               .w1c = (BIT(15) | BIT(5)) << 16,
   58 +               .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
   59 +       },
   60 +
   61 +       [PCI_EXP_SLTCAP2 / 4] = {
   62 +               /* Slot capabilities 2 register is reserved. */
   63 +       },
   64 +
   65 +       [PCI_EXP_SLTCTL2 / 4] = {
   66 +               /* Both Slot control 2 and Slot status 2 registers are reserved. */
   67 +       },
   68  };
   69  
   70  /*
   71 -- 
   72 2.32.0
   73