1 From b910f4b0beecc3e098da90390ac9fc36467937a9 Mon Sep 17 00:00:00 2001
    2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
    3 Date: Sun, 28 Mar 2021 14:34:49 +0200
    4 Subject: [PATCH 4/7] PCI: aardvark: Clear all MSIs at setup
    5 MIME-Version: 1.0
    6 Content-Type: text/plain; charset=UTF-8
    7 Content-Transfer-Encoding: 8bit
    8 
    9 We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).
   10 
   11 Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,
   12 to ensure that we don't start receiving spurious interrupts.
   13 
   14 Use this new mask in advk_pcie_handle_msi();
   15 
   16 Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
   17 Signed-off-by: Pali Rohár <pali@kernel.org>
   18 Signed-off-by: Marek Behún <kabel@kernel.org>
   19 Cc: stable@vger.kernel.org
   20 ---
   21  drivers/pci/controller/pci-aardvark.c | 6 ++++--
   22  1 file changed, 4 insertions(+), 2 deletions(-)
   23 
   24 diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
   25 index 25af189a1052..71ce9f02d596 100644
   26 --- a/drivers/pci/controller/pci-aardvark.c
   27 +++ b/drivers/pci/controller/pci-aardvark.c
   28 @@ -116,6 +116,7 @@
   29  #define PCIE_MSI_ADDR_HIGH_REG                 (CONTROL_BASE_ADDR + 0x54)
   30  #define PCIE_MSI_STATUS_REG                    (CONTROL_BASE_ADDR + 0x58)
   31  #define PCIE_MSI_MASK_REG                      (CONTROL_BASE_ADDR + 0x5C)
   32 +#define     PCIE_MSI_ALL_MASK                  GENMASK(31, 0)
   33  #define PCIE_MSI_PAYLOAD_REG                   (CONTROL_BASE_ADDR + 0x9C)
   34  #define     PCIE_MSI_DATA_MASK                 GENMASK(15, 0)
   35  
   36 @@ -571,6 +572,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
   37         advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
   38  
   39         /* Clear all interrupts */
   40 +       advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
   41         advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
   42         advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
   43         advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
   44 @@ -583,7 +585,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
   45         advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
   46  
   47         /* Unmask all MSIs */
   48 -       advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
   49 +       advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
   50  
   51         /* Enable summary interrupt for GIC SPI source */
   52         reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
   53 @@ -1399,7 +1401,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
   54  
   55         msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
   56         msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
   57 -       msi_status = msi_val & ~msi_mask;
   58 +       msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
   59  
   60         for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
   61                 if (!(BIT(msi_idx) & msi_status))
   62 -- 
   63 2.32.0
   64