1 From 015d52c7f64448591a741b00f178e173b9e54144 Mon Sep 17 00:00:00 2001 2 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz> 3 Date: Fri, 26 Oct 2018 00:15:41 +0200 4 Subject: [PATCH] Witi work 5 MIME-Version: 1.0 6 Content-Type: text/plain; charset=UTF-8 7 Content-Transfer-Encoding: 8bit 8 9 Signed-off-by: Marek Behún <marek.behun@nic.cz> 10 --- 11 arch/mips/ralink/Kconfig | 2 + 12 drivers/clk/mediatek/Kconfig | 17 +- 13 drivers/clk/mediatek/Makefile | 1 + 14 drivers/clk/mediatek/clk-mt7621-eth.c | 108 ++++ 15 drivers/clk/mediatek/clk-mt7621.c | 589 ++++++++++++++++++ 16 drivers/i2c/busses/Kconfig | 4 + 17 drivers/i2c/busses/Makefile | 1 + 18 drivers/i2c/busses/i2c-mt7621.c | 433 +++++++++++++ 19 drivers/net/ethernet/mediatek/Kconfig | 2 +- 20 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 94 ++- 21 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 9 + 22 drivers/staging/mt7621-pinctrl/Kconfig | 1 + 23 .../staging/mt7621-pinctrl/pinctrl-rt2880.c | 11 +- 24 drivers/watchdog/mt7621_wdt.c | 1 + 25 include/dt-bindings/clock/mt7621-clk.h | 37 ++ 26 15 files changed, 1286 insertions(+), 24 deletions(-) 27 create mode 100644 drivers/clk/mediatek/clk-mt7621-eth.c 28 create mode 100644 drivers/clk/mediatek/clk-mt7621.c 29 create mode 100644 drivers/i2c/busses/i2c-mt7621.c 30 create mode 100644 include/dt-bindings/clock/mt7621-clk.h 31 32 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig 33 index 1f9cb0e3c79a..b8fb38c11ce5 100644 34 --- a/arch/mips/ralink/Kconfig 35 +++ b/arch/mips/ralink/Kconfig 36 @@ -51,6 +51,8 @@ choice 37 select COMMON_CLK 38 select CLKSRC_MIPS_GIC 39 select HW_HAS_PCI 40 + select CLK_MT7621 41 + select CLK_MT7621_ETHSYS 42 endchoice 43 44 choice 45 diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig 46 index 3dd1dab92223..98b7344485c1 100644 47 --- a/drivers/clk/mediatek/Kconfig 48 +++ b/drivers/clk/mediatek/Kconfig 49 @@ -2,7 +2,7 @@ 50 # MediaTek Clock Drivers 51 # 52 menu "Clock driver for MediaTek SoC" 53 - depends on ARCH_MEDIATEK || COMPILE_TEST 54 + depends on ARCH_MEDIATEK || SOC_MT7621 || COMPILE_TEST 55 56 config COMMON_CLK_MEDIATEK 57 bool 58 @@ -193,4 +193,19 @@ config COMMON_CLK_MT8173 59 default ARCH_MEDIATEK 60 ---help--- 61 This driver supports MediaTek MT8173 clocks. 62 + 63 +config COMMON_CLK_MT7621 64 + bool "Clock driver for Mediatek MT7621" 65 + depends on SOC_MT7621 || COMPILE_TEST 66 + default SOC_MT7621 67 + ---help--- 68 + This driver supports Mediatek MT7621 basic clocks. 69 + 70 +config COMMON_CLK_MT7621_ETHSYS 71 + bool "Clock driver for Mediatek MT7621 ethsys" 72 + depends on COMMON_CLK_MT7621 73 + default SOC_MT7621 74 + select MFD_SYSCON 75 + ---help--- 76 + This driver supports Mediatek MT7621 ethsys clocks. 77 endmenu 78 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile 79 index 844b55d2770d..4bbc1a2def31 100644 80 --- a/drivers/clk/mediatek/Makefile 81 +++ b/drivers/clk/mediatek/Makefile 82 @@ -27,4 +27,5 @@ obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o 83 obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o 84 obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o 85 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o 86 +obj-$(CONFIG_COMMON_CLK_MT7621_ETHSYS) += clk-mtk.o clk-gate.o reset.o clk-mt7621-eth.o 87 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o 88 diff --git a/drivers/clk/mediatek/clk-mt7621-eth.c b/drivers/clk/mediatek/clk-mt7621-eth.c 89 new file mode 100644 90 index 000000000000..678d33900a0e 91 --- /dev/null 92 +++ b/drivers/clk/mediatek/clk-mt7621-eth.c 93 @@ -0,0 +1,108 @@ 94 +/* 95 + * Copyright (c) 2017 MediaTek Inc. 96 + * Author: Chen Zhong <chen.zhong@mediatek.com> 97 + * Sean Wang <sean.wang@mediatek.com> 98 + * 99 + * This program is free software; you can redistribute it and/or modify 100 + * it under the terms of the GNU General Public License version 2 as 101 + * published by the Free Software Foundation. 102 + * 103 + * This program is distributed in the hope that it will be useful, 104 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 105 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 106 + * GNU General Public License for more details. 107 + */ 108 + 109 +#include <linux/clk-provider.h> 110 +#include <linux/of.h> 111 +#include <linux/of_address.h> 112 +#include <linux/of_device.h> 113 +#include <linux/platform_device.h> 114 + 115 +#include "clk-mtk.h" 116 +#include "clk-gate.h" 117 + 118 +#include <dt-bindings/clock/mt7621-clk.h> 119 + 120 +#define GATE_ETH(_id, _name, _parent, _shift) { \ 121 + .id = _id, \ 122 + .name = _name, \ 123 + .parent_name = _parent, \ 124 + .regs = ð_cg_regs, \ 125 + .shift = _shift, \ 126 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 127 + } 128 + 129 +static const struct mtk_gate_regs eth_cg_regs = { 130 + .set_ofs = 0x30, 131 + .clr_ofs = 0x30, 132 + .sta_ofs = 0x30, 133 +}; 134 + 135 +static const struct mtk_gate eth_clks[] = { 136 + GATE_ETH(CLK_ETHSYS_HSDMA, "eth_hsdma_en", "clkxtal", 5), 137 + GATE_ETH(CLK_ETHSYS_ESW, "eth_esw_en", "clkxtal", 6), 138 + GATE_ETH(CLK_ETHSYS_GDMA, "eth_gdma_en", "clkxtal", 14), 139 + GATE_ETH(CLK_ETHSYS_I2C, "eth_i2c_en", "clkxtal", 16), 140 + GATE_ETH(CLK_ETHSYS_ETH, "eth_eth_en", "clkxtal", 23), 141 + GATE_ETH(CLK_ETHSYS_CRYPTO, "eth_crypto_en", "clkxtal", 29), 142 +}; 143 + 144 +static int clk_mt7621_ethsys_init(struct platform_device *pdev) 145 +{ 146 + struct clk_onecell_data *clk_data; 147 + struct device_node *node = pdev->dev.of_node; 148 + int r; 149 + 150 + clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); 151 + 152 + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), 153 + clk_data); 154 + 155 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 156 + if (r) 157 + dev_err(&pdev->dev, 158 + "could not register clock provider: %s: %d\n", 159 + pdev->name, r); 160 + 161 + mtk_register_reset_controller(node, 1, 0x34); 162 + 163 + return r; 164 +} 165 + 166 +static const struct of_device_id of_match_clk_mt7621_eth[] = { 167 + { 168 + .compatible = "mediatek,mt7621-ethsys", 169 + .data = clk_mt7621_ethsys_init, 170 + }, { 171 + /* sentinel */ 172 + } 173 +}; 174 + 175 +static int clk_mt7621_eth_probe(struct platform_device *pdev) 176 +{ 177 + int (*clk_init)(struct platform_device *); 178 + int r; 179 + 180 + clk_init = of_device_get_match_data(&pdev->dev); 181 + if (!clk_init) 182 + return -EINVAL; 183 + 184 + r = clk_init(pdev); 185 + if (r) 186 + dev_err(&pdev->dev, 187 + "could not register clock provider: %s: %d\n", 188 + pdev->name, r); 189 + 190 + return r; 191 +} 192 + 193 +static struct platform_driver clk_mt7621_eth_drv = { 194 + .probe = clk_mt7621_eth_probe, 195 + .driver = { 196 + .name = "clk-mt7621-eth", 197 + .of_match_table = of_match_clk_mt7621_eth, 198 + }, 199 +}; 200 + 201 +builtin_platform_driver(clk_mt7621_eth_drv); 202 diff --git a/drivers/clk/mediatek/clk-mt7621.c b/drivers/clk/mediatek/clk-mt7621.c 203 new file mode 100644 204 index 000000000000..0786ada35ede 205 --- /dev/null 206 +++ b/drivers/clk/mediatek/clk-mt7621.c 207 @@ -0,0 +1,589 @@ 208 +/* 209 + * Copyright (c) 2017 MediaTek Inc. 210 + * Author: Chen Zhong <chen.zhong@mediatek.com> 211 + * Sean Wang <sean.wang@mediatek.com> 212 + * 213 + * This program is free software; you can redistribute it and/or modify 214 + * it under the terms of the GNU General Public License version 2 as 215 + * published by the Free Software Foundation. 216 + * 217 + * This program is distributed in the hope that it will be useful, 218 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 219 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 220 + * GNU General Public License for more details. 221 + */ 222 + 223 +#include <linux/clk-provider.h> 224 +#include <linux/of.h> 225 +#include <linux/of_address.h> 226 +#include <linux/of_device.h> 227 +#include <linux/platform_device.h> 228 + 229 +#include "clk-mtk.h" 230 +#include "clk-gate.h" 231 +#include "clk-cpumux.h" 232 + 233 +#include <dt-bindings/clock/mt7621-clk.h> 234 +#include <linux/clk.h> /* for consumer */ 235 + 236 +#define MT7621_PLL_FMAX (2500UL * MHZ) 237 +#define CON0_MT7621_RST_BAR BIT(27) 238 + 239 +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ 240 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 241 + _pcw_shift, _div_table, _parent_name) { \ 242 + .id = _id, \ 243 + .name = _name, \ 244 + .reg = _reg, \ 245 + .pwr_reg = _pwr_reg, \ 246 + .en_mask = _en_mask, \ 247 + .flags = _flags, \ 248 + .rst_bar_mask = CON0_MT7621_RST_BAR, \ 249 + .fmax = MT7621_PLL_FMAX, \ 250 + .pcwbits = _pcwbits, \ 251 + .pd_reg = _pd_reg, \ 252 + .pd_shift = _pd_shift, \ 253 + .tuner_reg = _tuner_reg, \ 254 + .pcw_reg = _pcw_reg, \ 255 + .pcw_shift = _pcw_shift, \ 256 + .div_table = _div_table, \ 257 + .parent_name = _parent_name, \ 258 + } 259 + 260 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 261 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 262 + _pcw_shift) \ 263 + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ 264 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 265 + NULL, "clkxtal") 266 + 267 +#define GATE_APMIXED(_id, _name, _parent, _shift) { \ 268 + .id = _id, \ 269 + .name = _name, \ 270 + .parent_name = _parent, \ 271 + .regs = &apmixed_cg_regs, \ 272 + .shift = _shift, \ 273 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 274 + } 275 + 276 +#define GATE_INFRA(_id, _name, _parent, _shift) { \ 277 + .id = _id, \ 278 + .name = _name, \ 279 + .parent_name = _parent, \ 280 + .regs = &infra_cg_regs, \ 281 + .shift = _shift, \ 282 + .ops = &mtk_clk_gate_ops_setclr, \ 283 + } 284 + 285 +#define GATE_TOP0(_id, _name, _parent, _shift) { \ 286 + .id = _id, \ 287 + .name = _name, \ 288 + .parent_name = _parent, \ 289 + .regs = &top0_cg_regs, \ 290 + .shift = _shift, \ 291 + .ops = &mtk_clk_gate_ops_no_setclr, \ 292 + } 293 + 294 +#define GATE_TOP1(_id, _name, _parent, _shift) { \ 295 + .id = _id, \ 296 + .name = _name, \ 297 + .parent_name = _parent, \ 298 + .regs = &top1_cg_regs, \ 299 + .shift = _shift, \ 300 + .ops = &mtk_clk_gate_ops_no_setclr, \ 301 + } 302 + 303 +#define GATE_PERI0(_id, _name, _parent, _shift) { \ 304 + .id = _id, \ 305 + .name = _name, \ 306 + .parent_name = _parent, \ 307 + .regs = &peri0_cg_regs, \ 308 + .shift = _shift, \ 309 + .ops = &mtk_clk_gate_ops_setclr, \ 310 + } 311 + 312 +#define GATE_PERI1(_id, _name, _parent, _shift) { \ 313 + .id = _id, \ 314 + .name = _name, \ 315 + .parent_name = _parent, \ 316 + .regs = &peri1_cg_regs, \ 317 + .shift = _shift, \ 318 + .ops = &mtk_clk_gate_ops_setclr, \ 319 + } 320 + 321 +static DEFINE_SPINLOCK(mt7621_clk_lock); 322 + 323 +static const char * const infra_mux1_parents[] = { 324 + "clkxtal", 325 + "armpll", 326 + "main_core_en", 327 + "armpll" 328 +}; 329 + 330 +static const char * const axi_parents[] = { 331 + "clkxtal", 332 + "syspll1_d2", 333 + "syspll_d5", 334 + "syspll1_d4", 335 + "univpll_d5", 336 + "univpll2_d2", 337 + "univpll_d7" 338 +}; 339 + 340 +static const char * const mem_parents[] = { 341 + "clkxtal", 342 + "dmpll_ck" 343 +}; 344 + 345 +static const char * const ddrphycfg_parents[] = { 346 + "clkxtal", 347 + "syspll1_d8" 348 +}; 349 + 350 +static const char * const eth_parents[] = { 351 + "clkxtal", 352 + "ddrpll", 353 + "apll" 354 +}; 355 + 356 +static const char * const pwm_parents[] = { 357 + "clkxtal", 358 + "univpll2_d4" 359 +}; 360 + 361 +static const char * const f10m_ref_parents[] = { 362 + "clkxtal", 363 + "syspll4_d16" 364 +}; 365 + 366 +static const char * const nfi_infra_parents[] = { 367 + "clkxtal", 368 + "clkxtal", 369 + "clkxtal", 370 + "clkxtal", 371 + "clkxtal", 372 + "clkxtal", 373 + "clkxtal", 374 + "clkxtal", 375 + "univpll2_d8", 376 + "syspll1_d8", 377 + "univpll1_d8", 378 + "syspll4_d2", 379 + "univpll2_d4", 380 + "univpll3_d2", 381 + "syspll1_d4" 382 +}; 383 + 384 +static const char * const flash_parents[] = { 385 + "clkxtal", 386 + "univpll_d80_d4", 387 + "syspll2_d8", 388 + "syspll3_d4", 389 + "univpll3_d4", 390 + "univpll1_d8", 391 + "syspll2_d4", 392 + "univpll2_d4" 393 +}; 394 + 395 +static const char * const uart_parents[] = { 396 + "clkxtal", 397 + "univpll2_d8" 398 +}; 399 + 400 +static const char * const spi0_parents[] = { 401 + "clkxtal", 402 + "syspll3_d2", 403 + "clkxtal", 404 + "syspll2_d4", 405 + "syspll4_d2", 406 + "univpll2_d4", 407 + "univpll1_d8", 408 + "clkxtal" 409 +}; 410 + 411 +static const char * const spi1_parents[] = { 412 + "clkxtal", 413 + "syspll3_d2", 414 + "clkxtal", 415 + "syspll4_d4", 416 + "syspll4_d2", 417 + "univpll2_d4", 418 + "univpll1_d8", 419 + "clkxtal" 420 +}; 421 + 422 +static const char * const msdc30_0_parents[] = { 423 + "clkxtal", 424 + "univpll2_d16", 425 + "univ48m" 426 +}; 427 + 428 +static const char * const a1sys_hp_parents[] = { 429 + "clkxtal", 430 + "aud1pll_ck", 431 + "aud2pll_ck", 432 + "clkxtal" 433 +}; 434 + 435 +static const char * const intdir_parents[] = { 436 + "clkxtal", 437 + "syspll_d2", 438 + "univpll_d2", 439 + "sgmiipll_ck" 440 +}; 441 + 442 +static const char * const aud_intbus_parents[] = { 443 + "clkxtal", 444 + "syspll1_d4", 445 + "syspll4_d2", 446 + "syspll3_d2" 447 +}; 448 + 449 +static const char * const pmicspi_parents[] = { 450 + "clkxtal", 451 + "clk_null", 452 + "clk_null", 453 + "clk_null", 454 + "clk_null", 455 + "univpll2_d16" 456 +}; 457 + 458 +static const char * const atb_parents[] = { 459 + "clkxtal", 460 + "syspll1_d2", 461 + "syspll_d5" 462 +}; 463 + 464 +static const char * const audio_parents[] = { 465 + "clkxtal", 466 + "syspll3_d4", 467 + "syspll4_d4", 468 + "univpll1_d16" 469 +}; 470 + 471 +static const char * const usb20_parents[] = { 472 + "clkxtal", 473 + "univpll3_d4", 474 + "syspll1_d8", 475 + "clkxtal" 476 +}; 477 + 478 +static const char * const aud1_parents[] = { 479 + "clkxtal", 480 + "aud1pll_ck" 481 +}; 482 + 483 +static const char * const aud2_parents[] = { 484 + "clkxtal", 485 + "aud2pll_ck" 486 +}; 487 + 488 +static const char * const asm_l_parents[] = { 489 + "clkxtal", 490 + "syspll_d5", 491 + "univpll2_d2", 492 + "univpll2_d4" 493 +}; 494 + 495 +static const char * const apll1_ck_parents[] = { 496 + "aud1_sel", 497 + "aud2_sel" 498 +}; 499 + 500 +static const char * const peribus_ck_parents[] = { 501 + "syspll1_d8", 502 + "syspll1_d4" 503 +}; 504 + 505 +static const struct mtk_gate_regs apmixed_cg_regs = { 506 + .set_ofs = 0x8, 507 + .clr_ofs = 0x8, 508 + .sta_ofs = 0x8, 509 +}; 510 + 511 +static const struct mtk_gate_regs infra_cg_regs = { 512 + .set_ofs = 0x40, 513 + .clr_ofs = 0x44, 514 + .sta_ofs = 0x48, 515 +}; 516 + 517 +static const struct mtk_gate_regs top0_cg_regs = { 518 + .set_ofs = 0x120, 519 + .clr_ofs = 0x120, 520 + .sta_ofs = 0x120, 521 +}; 522 + 523 +static const struct mtk_gate_regs top1_cg_regs = { 524 + .set_ofs = 0x128, 525 + .clr_ofs = 0x128, 526 + .sta_ofs = 0x128, 527 +}; 528 + 529 +static const struct mtk_gate_regs peri0_cg_regs = { 530 + .set_ofs = 0x8, 531 + .clr_ofs = 0x10, 532 + .sta_ofs = 0x18, 533 +}; 534 + 535 +static const struct mtk_gate_regs peri1_cg_regs = { 536 + .set_ofs = 0xC, 537 + .clr_ofs = 0x14, 538 + .sta_ofs = 0x1C, 539 +}; 540 + 541 +static const struct mtk_pll_data plls[] = { 542 + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 543 + PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), 544 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001, 545 + HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), 546 + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001, 547 + HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), 548 + PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001, 549 + 0, 21, 0x0300, 1, 0, 0x0304, 0), 550 + PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001, 551 + 0, 21, 0x0314, 1, 0, 0x0318, 0), 552 + PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001, 553 + 0, 31, 0x0324, 1, 0, 0x0328, 0), 554 + PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001, 555 + 0, 31, 0x0334, 1, 0, 0x0338, 0), 556 + PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001, 557 + 0, 21, 0x0344, 1, 0, 0x0348, 0), 558 + PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001, 559 + 0, 21, 0x0358, 1, 0, 0x035C, 0), 560 +}; 561 + 562 +static const struct mtk_gate apmixed_clks[] = { 563 + GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), 564 +}; 565 + 566 +static const struct mtk_gate infra_clks[] = { 567 + GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), 568 + GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), 569 + GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5), 570 + GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16), 571 + GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18), 572 + GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22), 573 +}; 574 + 575 +static const struct mtk_fixed_clk top_fixed_clks[] = { 576 + FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 577 + 31250000), 578 +}; 579 + 580 +static const struct mtk_fixed_factor top_divs[] = { 581 + FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), 582 + FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), 583 + FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), 584 + FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), 585 + FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), 586 + FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), 587 + FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), 588 + FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 589 + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 590 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 591 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 592 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 593 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 594 + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 595 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 596 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 597 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 598 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 599 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 600 + FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), 601 + FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), 602 + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 603 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 604 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 605 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), 606 + FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32), 607 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 608 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 609 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 610 + FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), 611 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 612 + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 613 + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 614 + FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), 615 + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 616 + FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), 617 + FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), 618 + FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1), 619 + FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), 620 + FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1), 621 + FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1), 622 + FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2), 623 + FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4), 624 + FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1), 625 + FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1), 626 + FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), 627 +}; 628 + 629 +static const struct mtk_gate top_clks[] = { 630 + /* TOP0 */ 631 + GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0), 632 + GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1), 633 + GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div", 634 + 2), 635 + GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div", 636 + 3), 637 + GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div", 638 + 4), 639 + GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div", 640 + 5), 641 + 642 + /* TOP1 */ 643 + GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0), 644 + GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16), 645 +}; 646 + 647 +static const struct mtk_clk_divider top_adj_divs[] = { 648 + DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel", 649 + 0x120, 24, 3), 650 + DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel", 651 + 0x120, 28, 3), 652 + DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel", 653 + 0x124, 0, 7), 654 + DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel", 655 + 0x124, 8, 7), 656 + DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck", 657 + 0x124, 16, 7), 658 + DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel", 659 + 0x124, 24, 7), 660 + DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel", 661 + 0x128, 8, 7), 662 + DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel", 663 + 0x128, 24, 7), 664 +}; 665 + 666 +static const struct mtk_gate peri_clks[] = { 667 + /* PERI0 */ 668 + GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1), 669 + GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2), 670 + GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3), 671 + GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4), 672 + GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5), 673 + GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6), 674 + GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7), 675 + GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8), 676 + GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9), 677 + GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12), 678 + GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13), 679 + GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14), 680 + GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), 681 + GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18), 682 + GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19), 683 + GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20), 684 + GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21), 685 + GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22), 686 + GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23), 687 + GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24), 688 + GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25), 689 + GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26), 690 + GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27), 691 + GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28), 692 + GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29), 693 + GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30), 694 + GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31), 695 + 696 + /* PERI1 */ 697 + GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1), 698 + GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2), 699 +}; 700 + 701 +static struct mtk_composite infra_muxes[] __initdata = { 702 + MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 703 + 0x000, 2, 2), 704 +}; 705 + 706 +static struct mtk_composite top_muxes[] = { 707 + /* CLK_CFG_0 */ 708 + MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 709 + 0x040, 24, 3, 31), 710 +}; 711 + 712 +static struct mtk_composite peri_muxes[] = { 713 + /* PERI_GLOBALCON_CKSEL */ 714 + MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), 715 +}; 716 + 717 +static int mtk_topckgen_init(struct platform_device *pdev) 718 +{ 719 + struct clk_onecell_data *clk_data; 720 + void __iomem *base; 721 + struct device_node *node = pdev->dev.of_node; 722 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 723 + 724 + base = devm_ioremap_resource(&pdev->dev, res); 725 + if (IS_ERR(base)) 726 + return PTR_ERR(base); 727 + 728 + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 729 + 730 + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 731 + clk_data); 732 + 733 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), 734 + clk_data); 735 + 736 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), 737 + base, &mt7621_clk_lock, clk_data); 738 + 739 + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 740 + base, &mt7621_clk_lock, clk_data); 741 + 742 + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 743 + clk_data); 744 + 745 + clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); 746 + clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); 747 + clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); 748 + 749 + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 750 +} 751 + 752 +static const struct of_device_id of_match_clk_mt7621[] = { 753 + { 754 + .compatible = "mediatek,mt7621-topckgen", 755 + .data = mtk_topckgen_init, 756 + }, { 757 + /* sentinel */ 758 + } 759 +}; 760 + 761 +static int clk_mt7621_probe(struct platform_device *pdev) 762 +{ 763 + int (*clk_init)(struct platform_device *); 764 + int r; 765 + 766 + dev_err(&pdev->dev, "clk_mt7621_probe\n"); 767 + 768 + clk_init = of_device_get_match_data(&pdev->dev); 769 + if (!clk_init) { 770 + dev_err(&pdev->dev, "clk_mt7621_probe failed\n"); 771 + return -EINVAL; 772 + }; 773 + 774 + r = clk_init(pdev); 775 + if (r) 776 + dev_err(&pdev->dev, 777 + "could not register clock provider: %s: %d\n", 778 + pdev->name, r); 779 + 780 + return r; 781 +} 782 + 783 +static struct platform_driver clk_mt7621_drv = { 784 + .probe = clk_mt7621_probe, 785 + .driver = { 786 + .name = "clk-mt7621", 787 + .of_match_table = of_match_clk_mt7621, 788 + }, 789 +}; 790 + 791 +static int clk_mt7621_init(void) 792 +{ 793 + return platform_driver_register(&clk_mt7621_drv); 794 +} 795 + 796 +arch_initcall(clk_mt7621_init); 797 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig 798 index 451d4ae50e66..db8408506e91 100644 799 --- a/drivers/i2c/busses/Kconfig 800 +++ b/drivers/i2c/busses/Kconfig 801 @@ -709,6 +709,10 @@ config I2C_MT65XX 802 If you want to use MediaTek(R) I2C interface, say Y or M here. 803 If unsure, say N. 804 805 +config I2C_MT7621 806 + tristate "MediaTek MT7621/MT7628 I2C Controller" 807 + depends on OF && (ARCH_MEDIATEK || SOC_MT7621) 808 + 809 config I2C_MV64XXX 810 tristate "Marvell mv64xxx I2C Controller" 811 depends on MV64X60 || PLAT_ORION || ARCH_SUNXI || ARCH_MVEBU 812 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile 813 index 18b26af82b1c..35c8fa744027 100644 814 --- a/drivers/i2c/busses/Makefile 815 +++ b/drivers/i2c/busses/Makefile 816 @@ -71,6 +71,7 @@ obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o 817 obj-$(CONFIG_I2C_MESON) += i2c-meson.o 818 obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 819 obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o 820 +obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o 821 obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 822 obj-$(CONFIG_I2C_MXS) += i2c-mxs.o 823 obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o 824 diff --git a/drivers/i2c/busses/i2c-mt7621.c b/drivers/i2c/busses/i2c-mt7621.c 825 new file mode 100644 826 index 000000000000..e2849e849d32 827 --- /dev/null 828 +++ b/drivers/i2c/busses/i2c-mt7621.c 829 @@ -0,0 +1,433 @@ 830 +/* 831 + * drivers/i2c/busses/i2c-mt7621.c 832 + * 833 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com> 834 + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com> 835 + * 836 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus. 837 + * (C) 2014 Sittisak <sittisaks@hotmail.com> 838 + * 839 + * This software is licensed under the terms of the GNU General Public 840 + * License version 2, as published by the Free Software Foundation, and 841 + * may be copied, distributed, and modified under those terms. 842 + * 843 + * This program is distributed in the hope that it will be useful, 844 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 845 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 846 + * GNU General Public License for more details. 847 + * 848 + */ 849 + 850 +#include <linux/interrupt.h> 851 +#include <linux/kernel.h> 852 +#include <linux/module.h> 853 +#include <linux/reset.h> 854 +#include <linux/delay.h> 855 +#include <linux/slab.h> 856 +#include <linux/init.h> 857 +#include <linux/errno.h> 858 +#include <linux/platform_device.h> 859 +#include <linux/of_platform.h> 860 +#include <linux/i2c.h> 861 +#include <linux/io.h> 862 +#include <linux/err.h> 863 +#include <linux/clk.h> 864 + 865 +#define REG_SM0CFG0 0x08 866 +#define REG_SM0DOUT 0x10 867 +#define REG_SM0DIN 0x14 868 +#define REG_SM0ST 0x18 869 +#define REG_SM0AUTO 0x1C 870 +#define REG_SM0CFG1 0x20 871 +#define REG_SM0CFG2 0x28 872 +#define REG_SM0CTL0 0x40 873 +#define REG_SM0CTL1 0x44 874 +#define REG_SM0D0 0x50 875 +#define REG_SM0D1 0x54 876 +#define REG_PINTEN 0x5C 877 +#define REG_PINTST 0x60 878 +#define REG_PINTCL 0x64 879 + 880 +/* REG_SM0CFG0 */ 881 +#define I2C_DEVADDR_MASK 0x7f 882 + 883 +/* REG_SM0ST */ 884 +#define I2C_DATARDY BIT(2) 885 +#define I2C_SDOEMPTY BIT(1) 886 +#define I2C_BUSY BIT(0) 887 + 888 +/* REG_SM0AUTO */ 889 +#define READ_CMD BIT(0) 890 + 891 +/* REG_SM0CFG1 */ 892 +#define BYTECNT_MAX 64 893 +#define SET_BYTECNT(x) (x - 1) 894 + 895 +/* REG_SM0CFG2 */ 896 +#define AUTOMODE_EN BIT(0) 897 + 898 +/* REG_SM0CTL0 */ 899 +#define ODRAIN_HIGH_SM0 BIT(31) 900 +#define VSYNC_SHIFT 28 901 +#define VSYNC_MASK 0x3 902 +#define VSYNC_PULSE (0x1 << VSYNC_SHIFT) 903 +#define VSYNC_RISING (0x2 << VSYNC_SHIFT) 904 +#define CLK_DIV_SHIFT 16 905 +#define CLK_DIV_MASK 0xfff 906 +#define DEG_CNT_SHIFT 8 907 +#define DEG_CNT_MASK 0xff 908 +#define WAIT_HIGH BIT(6) 909 +#define DEG_EN BIT(5) 910 +#define CS_STATUA BIT(4) 911 +#define SCL_STATUS BIT(3) 912 +#define SDA_STATUS BIT(2) 913 +#define SM0_EN BIT(1) 914 +#define SCL_STRECH BIT(0) 915 + 916 +/* REG_SM0CTL1 */ 917 +#define ACK_SHIFT 16 918 +#define ACK_MASK 0xff 919 +#define PGLEN_SHIFT 8 920 +#define PGLEN_MASK 0x7 921 +#define SM0_MODE_SHIFT 4 922 +#define SM0_MODE_MASK 0x7 923 +#define SM0_MODE_START 0x1 924 +#define SM0_MODE_WRITE 0x2 925 +#define SM0_MODE_STOP 0x3 926 +#define SM0_MODE_READ_NACK 0x4 927 +#define SM0_MODE_READ_ACK 0x5 928 +#define SM0_TRI_BUSY BIT(0) 929 + 930 +/* timeout waiting for I2C devices to respond (clock streching) */ 931 +#define TIMEOUT_MS 1000 932 +#define DELAY_INTERVAL_US 100 933 + 934 +struct mtk_i2c { 935 + void __iomem *base; 936 + struct clk *clk; 937 + struct device *dev; 938 + struct i2c_adapter adap; 939 + u32 cur_clk; 940 + u32 clk_div; 941 + u32 flags; 942 +}; 943 + 944 +static void mtk_i2c_w32(struct mtk_i2c *i2c, u32 val, unsigned reg) 945 +{ 946 + iowrite32(val, i2c->base + reg); 947 +} 948 + 949 +static u32 mtk_i2c_r32(struct mtk_i2c *i2c, unsigned reg) 950 +{ 951 + return ioread32(i2c->base + reg); 952 +} 953 + 954 +static int poll_down_timeout(void __iomem *addr, u32 mask) 955 +{ 956 + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); 957 + 958 + do { 959 + if (!(readl_relaxed(addr) & mask)) 960 + return 0; 961 + 962 + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); 963 + } while (time_before(jiffies, timeout)); 964 + 965 + return (readl_relaxed(addr) & mask) ? -EAGAIN : 0; 966 +} 967 + 968 +static int mtk_i2c_wait_idle(struct mtk_i2c *i2c) 969 +{ 970 + int ret; 971 + 972 + ret = poll_down_timeout(i2c->base + REG_SM0ST, I2C_BUSY); 973 + if (ret < 0) 974 + dev_dbg(i2c->dev, "idle err(%d)\n", ret); 975 + 976 + return ret; 977 +} 978 + 979 +static int poll_up_timeout(void __iomem *addr, u32 mask) 980 +{ 981 + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); 982 + u32 status; 983 + 984 + do { 985 + status = readl_relaxed(addr); 986 + if (status & mask) 987 + return 0; 988 + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); 989 + } while (time_before(jiffies, timeout)); 990 + 991 + return -ETIMEDOUT; 992 +} 993 + 994 +static int mtk_i2c_wait_rx_done(struct mtk_i2c *i2c) 995 +{ 996 + int ret; 997 + 998 + ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_DATARDY); 999 + if (ret < 0) 1000 + dev_dbg(i2c->dev, "rx err(%d)\n", ret); 1001 + 1002 + return ret; 1003 +} 1004 + 1005 +static int mtk_i2c_wait_tx_done(struct mtk_i2c *i2c) 1006 +{ 1007 + int ret; 1008 + 1009 + ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_SDOEMPTY); 1010 + if (ret < 0) 1011 + dev_dbg(i2c->dev, "tx err(%d)\n", ret); 1012 + 1013 + return ret; 1014 +} 1015 + 1016 +static void mtk_i2c_reset(struct mtk_i2c *i2c) 1017 +{ 1018 + u32 reg; 1019 + device_reset(i2c->adap.dev.parent); 1020 + barrier(); 1021 + 1022 + /* ctrl0 */ 1023 + reg = ODRAIN_HIGH_SM0 | VSYNC_PULSE | (i2c->clk_div << CLK_DIV_SHIFT) | 1024 + WAIT_HIGH | SM0_EN; 1025 + mtk_i2c_w32(i2c, reg, REG_SM0CTL0); 1026 + 1027 + /* auto mode */ 1028 + mtk_i2c_w32(i2c, AUTOMODE_EN, REG_SM0CFG2); 1029 +} 1030 + 1031 +static void mtk_i2c_dump_reg(struct mtk_i2c *i2c) 1032 +{ 1033 + dev_dbg(i2c->dev, "cfg0 %08x, dout %08x, din %08x, " \ 1034 + "status %08x, auto %08x, cfg1 %08x, " \ 1035 + "cfg2 %08x, ctl0 %08x, ctl1 %08x\n", 1036 + mtk_i2c_r32(i2c, REG_SM0CFG0), 1037 + mtk_i2c_r32(i2c, REG_SM0DOUT), 1038 + mtk_i2c_r32(i2c, REG_SM0DIN), 1039 + mtk_i2c_r32(i2c, REG_SM0ST), 1040 + mtk_i2c_r32(i2c, REG_SM0AUTO), 1041 + mtk_i2c_r32(i2c, REG_SM0CFG1), 1042 + mtk_i2c_r32(i2c, REG_SM0CFG2), 1043 + mtk_i2c_r32(i2c, REG_SM0CTL0), 1044 + mtk_i2c_r32(i2c, REG_SM0CTL1)); 1045 +} 1046 + 1047 +static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 1048 + int num) 1049 +{ 1050 + struct mtk_i2c *i2c; 1051 + struct i2c_msg *pmsg; 1052 + int i, j, ret; 1053 + u32 cmd; 1054 + 1055 + i2c = i2c_get_adapdata(adap); 1056 + 1057 + for (i = 0; i < num; i++) { 1058 + pmsg = &msgs[i]; 1059 + cmd = 0; 1060 + 1061 + dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x\n", 1062 + pmsg->addr, pmsg->len, pmsg->flags); 1063 + 1064 + /* wait hardware idle */ 1065 + if ((ret = mtk_i2c_wait_idle(i2c))) 1066 + goto err_timeout; 1067 + 1068 + if (pmsg->flags & I2C_M_TEN) { 1069 + dev_dbg(i2c->dev, "10 bits addr not supported\n"); 1070 + return -EINVAL; 1071 + } else { 1072 + /* 7 bits address */ 1073 + mtk_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK, 1074 + REG_SM0CFG0); 1075 + } 1076 + 1077 + /* buffer length */ 1078 + if (pmsg->len == 0) { 1079 + dev_dbg(i2c->dev, "length is 0\n"); 1080 + return -EINVAL; 1081 + } else 1082 + mtk_i2c_w32(i2c, SET_BYTECNT(pmsg->len), 1083 + REG_SM0CFG1); 1084 + 1085 + j = 0; 1086 + if (pmsg->flags & I2C_M_RD) { 1087 + cmd |= READ_CMD; 1088 + /* start transfer */ 1089 + barrier(); 1090 + mtk_i2c_w32(i2c, cmd, REG_SM0AUTO); 1091 + do { 1092 + /* wait */ 1093 + if ((ret = mtk_i2c_wait_rx_done(i2c))) 1094 + goto err_timeout; 1095 + /* read data */ 1096 + if (pmsg->len) 1097 + pmsg->buf[j] = mtk_i2c_r32(i2c, 1098 + REG_SM0DIN); 1099 + j++; 1100 + } while (j < pmsg->len); 1101 + } else { 1102 + do { 1103 + /* write data */ 1104 + if (pmsg->len) 1105 + mtk_i2c_w32(i2c, pmsg->buf[j], 1106 + REG_SM0DOUT); 1107 + /* start transfer */ 1108 + if (j == 0) { 1109 + barrier(); 1110 + mtk_i2c_w32(i2c, cmd, REG_SM0AUTO); 1111 + } 1112 + /* wait */ 1113 + if ((ret = mtk_i2c_wait_tx_done(i2c))) 1114 + goto err_timeout; 1115 + j++; 1116 + } while (j < pmsg->len); 1117 + } 1118 + } 1119 + /* the return value is number of executed messages */ 1120 + ret = i; 1121 + 1122 + return ret; 1123 + 1124 +err_timeout: 1125 + mtk_i2c_dump_reg(i2c); 1126 + mtk_i2c_reset(i2c); 1127 + return ret; 1128 +} 1129 + 1130 +static u32 mtk_i2c_func(struct i2c_adapter *a) 1131 +{ 1132 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1133 +} 1134 + 1135 +static const struct i2c_algorithm mtk_i2c_algo = { 1136 + .master_xfer = mtk_i2c_master_xfer, 1137 + .functionality = mtk_i2c_func, 1138 +}; 1139 + 1140 +static const struct of_device_id i2c_mtk_dt_ids[] = { 1141 + { .compatible = "mediatek,mt7621-i2c" }, 1142 + { /* sentinel */ } 1143 +}; 1144 + 1145 +MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids); 1146 + 1147 +static struct i2c_adapter_quirks mtk_i2c_quirks = { 1148 + .max_write_len = BYTECNT_MAX, 1149 + .max_read_len = BYTECNT_MAX, 1150 +}; 1151 + 1152 +static void mtk_i2c_init(struct mtk_i2c *i2c) 1153 +{ 1154 + i2c->clk_div = clk_get_rate(i2c->clk) / i2c->cur_clk; 1155 + if (i2c->clk_div > CLK_DIV_MASK) 1156 + i2c->clk_div = CLK_DIV_MASK; 1157 + 1158 + mtk_i2c_reset(i2c); 1159 +} 1160 + 1161 +static int mtk_i2c_probe(struct platform_device *pdev) 1162 +{ 1163 + struct resource *res; 1164 + struct mtk_i2c *i2c; 1165 + struct i2c_adapter *adap; 1166 + const struct of_device_id *match; 1167 + int ret; 1168 + 1169 + match = of_match_device(i2c_mtk_dt_ids, &pdev->dev); 1170 + 1171 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1172 + if (!res) { 1173 + dev_err(&pdev->dev, "no memory resource found\n"); 1174 + return -ENODEV; 1175 + } 1176 + 1177 + i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL); 1178 + if (!i2c) { 1179 + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n"); 1180 + return -ENOMEM; 1181 + } 1182 + 1183 + i2c->base = devm_ioremap_resource(&pdev->dev, res); 1184 + if (IS_ERR(i2c->base)) 1185 + return PTR_ERR(i2c->base); 1186 + 1187 + i2c->clk = devm_clk_get(&pdev->dev, NULL); 1188 + if (IS_ERR(i2c->clk)) { 1189 + dev_err(&pdev->dev, "no clock defined\n"); 1190 + return -ENODEV; 1191 + } 1192 + clk_prepare_enable(i2c->clk); 1193 + i2c->dev = &pdev->dev; 1194 + 1195 + if (of_property_read_u32(pdev->dev.of_node, 1196 + "clock-frequency", &i2c->cur_clk)) 1197 + i2c->cur_clk = 100000; 1198 + 1199 + adap = &i2c->adap; 1200 + adap->owner = THIS_MODULE; 1201 + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1202 + adap->algo = &mtk_i2c_algo; 1203 + adap->retries = 3; 1204 + adap->dev.parent = &pdev->dev; 1205 + i2c_set_adapdata(adap, i2c); 1206 + adap->dev.of_node = pdev->dev.of_node; 1207 + strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); 1208 + adap->quirks = &mtk_i2c_quirks; 1209 + 1210 + platform_set_drvdata(pdev, i2c); 1211 + 1212 + mtk_i2c_init(i2c); 1213 + 1214 + ret = i2c_add_adapter(adap); 1215 + if (ret < 0) { 1216 + dev_err(&pdev->dev, "failed to add adapter\n"); 1217 + clk_disable_unprepare(i2c->clk); 1218 + return ret; 1219 + } 1220 + 1221 + dev_info(&pdev->dev, "clock %uKHz, re-start not support\n", 1222 + i2c->cur_clk/1000); 1223 + 1224 + return ret; 1225 +} 1226 + 1227 +static int mtk_i2c_remove(struct platform_device *pdev) 1228 +{ 1229 + struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1230 + 1231 + i2c_del_adapter(&i2c->adap); 1232 + clk_disable_unprepare(i2c->clk); 1233 + 1234 + return 0; 1235 +} 1236 + 1237 +static struct platform_driver mtk_i2c_driver = { 1238 + .probe = mtk_i2c_probe, 1239 + .remove = mtk_i2c_remove, 1240 + .driver = { 1241 + .owner = THIS_MODULE, 1242 + .name = "i2c-mt7621", 1243 + .of_match_table = i2c_mtk_dt_ids, 1244 + }, 1245 +}; 1246 + 1247 +static int __init i2c_mtk_init (void) 1248 +{ 1249 + return platform_driver_register(&mtk_i2c_driver); 1250 +} 1251 +subsys_initcall(i2c_mtk_init); 1252 + 1253 +static void __exit i2c_mtk_exit (void) 1254 +{ 1255 + platform_driver_unregister(&mtk_i2c_driver); 1256 +} 1257 +module_exit(i2c_mtk_exit); 1258 + 1259 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>"); 1260 +MODULE_DESCRIPTION("MT7621 I2c host driver"); 1261 +MODULE_LICENSE("GPL"); 1262 +MODULE_ALIAS("platform:MT7621-I2C"); 1263 diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig 1264 index f9149d2a4694..43656f961891 100644 1265 --- a/drivers/net/ethernet/mediatek/Kconfig 1266 +++ b/drivers/net/ethernet/mediatek/Kconfig 1267 @@ -1,6 +1,6 @@ 1268 config NET_VENDOR_MEDIATEK 1269 bool "MediaTek ethernet driver" 1270 - depends on ARCH_MEDIATEK 1271 + depends on ARCH_MEDIATEK || SOC_MT7621 1272 ---help--- 1273 If you have a Mediatek SoC with ethernet, say Y. 1274 1275 diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c 1276 index 7dbfdac4067a..e830a733efab 100644 1277 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 1278 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c 1279 @@ -147,14 +147,17 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 1280 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 1281 mtk_w32(eth, val, INTF_MODE); 1282 1283 - regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 1284 - ETHSYS_TRGMII_CLK_SEL362_5, 1285 - ETHSYS_TRGMII_CLK_SEL362_5); 1286 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_TRGMII)) { 1287 + regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 1288 + ETHSYS_TRGMII_CLK_SEL362_5, 1289 + ETHSYS_TRGMII_CLK_SEL362_5); 1290 1291 - val = (speed == SPEED_1000) ? 250000000 : 500000000; 1292 - ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 1293 - if (ret) 1294 - dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 1295 + val = (speed == SPEED_1000) ? 250000000 : 500000000; 1296 + ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 1297 + if (ret) 1298 + dev_err(eth->dev, "Failed to set trgmii pll: %d\n", 1299 + ret); 1300 + } 1301 1302 val = (speed == SPEED_1000) ? 1303 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 1304 @@ -1760,6 +1763,26 @@ static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1305 return IRQ_HANDLED; 1306 } 1307 1308 +static irqreturn_t mtk_handle_irq(int irq, void *_eth) 1309 +{ 1310 + u32 status; 1311 + struct mtk_eth *eth = _eth; 1312 + 1313 + status = mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT; 1314 + status |= mtk_r32(eth, MTK_QMTK_INT_STATUS) & MTK_TX_DONE_INT; 1315 + 1316 + if (!status) 1317 + return IRQ_NONE; 1318 + 1319 + if (status & MTK_RX_DONE_INT) 1320 + mtk_handle_irq_rx(irq, _eth); 1321 + 1322 + if (status & MTK_TX_DONE_INT) 1323 + mtk_handle_irq_tx(irq, _eth); 1324 + 1325 + return IRQ_HANDLED; 1326 +} 1327 + 1328 #ifdef CONFIG_NET_POLL_CONTROLLER 1329 static void mtk_poll_controller(struct net_device *dev) 1330 { 1331 @@ -1768,7 +1791,10 @@ static void mtk_poll_controller(struct net_device *dev) 1332 1333 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1334 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1335 - mtk_handle_irq_rx(eth->irq[2], dev); 1336 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SINGLE_IRQ)) 1337 + mtk_handle_irq(eth->irq[0], eth); 1338 + else 1339 + mtk_handle_irq_rx(eth->irq[2], eth); 1340 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1341 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1342 } 1343 @@ -1940,6 +1966,19 @@ static int mtk_hw_init(struct mtk_eth *eth) 1344 } 1345 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1346 1347 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII_PAD)) { 1348 + regmap_read(eth->ethsys, ETHSYS_RGMII_PAD, &val); 1349 + val &= ~RGMII_PAD_MDIO_DRV_MASK; 1350 + regmap_write(eth->ethsys, ETHSYS_RGMII_PAD, val); 1351 + } 1352 + 1353 +/* if (MTK_HAS_CAPS(eth->soc->caps, MTK_GPIO_MODE)) { 1354 + regmap_read(eth->ethsys, ETHSYS_GPIO_MODE, &val); 1355 + val &= ~GPIO_MODE(GPIO_MODE_MASK, 0); 1356 + val &= ~GPIO_MODE(GPIO_MODE_MASK, 1); 1357 + regmap_write(eth->ethsys, ETHSYS_GPIO_MODE, val); 1358 + }*/ 1359 + 1360 if (eth->pctl) { 1361 /* Set GE2 driving and slew rate */ 1362 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1363 @@ -2456,7 +2495,7 @@ static int mtk_probe(struct platform_device *pdev) 1364 struct device_node *mac_np; 1365 struct mtk_eth *eth; 1366 int err; 1367 - int i; 1368 + int i, nirqs; 1369 1370 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 1371 if (!eth) 1372 @@ -2499,7 +2538,12 @@ static int mtk_probe(struct platform_device *pdev) 1373 } 1374 } 1375 1376 - for (i = 0; i < 3; i++) { 1377 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SINGLE_IRQ)) 1378 + nirqs = 1; 1379 + else 1380 + nirqs = 3; 1381 + 1382 + for (i = 0; i < nirqs; i++) { 1383 eth->irq[i] = platform_get_irq(pdev, i); 1384 if (eth->irq[i] < 0) { 1385 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 1386 @@ -2543,15 +2587,22 @@ static int mtk_probe(struct platform_device *pdev) 1387 goto err_deinit_hw; 1388 } 1389 1390 - err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0, 1391 - dev_name(eth->dev), eth); 1392 - if (err) 1393 - goto err_free_dev; 1394 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SINGLE_IRQ)) { 1395 + err = devm_request_irq(eth->dev, eth->irq[0], mtk_handle_irq, 0, 1396 + dev_name(eth->dev), eth); 1397 + if (err) 1398 + goto err_free_dev; 1399 + } else { 1400 + err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 1401 + 0, dev_name(eth->dev), eth); 1402 + if (err) 1403 + goto err_free_dev; 1404 1405 - err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0, 1406 - dev_name(eth->dev), eth); 1407 - if (err) 1408 - goto err_free_dev; 1409 + err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 1410 + 0, dev_name(eth->dev), eth); 1411 + if (err) 1412 + goto err_free_dev; 1413 + } 1414 1415 err = mtk_mdio_init(eth); 1416 if (err) 1417 @@ -2622,6 +2673,12 @@ static const struct mtk_soc_data mt2701_data = { 1418 .required_pctl = true, 1419 }; 1420 1421 +static const struct mtk_soc_data mt7621_data = { 1422 + .caps = MTK_MT7621 | MTK_HWLRO, 1423 + .required_clks = MT7621_CLKS_BITMAP, 1424 + .required_pctl = false, 1425 +}; 1426 + 1427 static const struct mtk_soc_data mt7622_data = { 1428 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO, 1429 .required_clks = MT7622_CLKS_BITMAP, 1430 @@ -2636,6 +2693,7 @@ static const struct mtk_soc_data mt7623_data = { 1431 1432 const struct of_device_id of_mtk_match[] = { 1433 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 1434 + { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 1435 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 1436 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 1437 {}, 1438 diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h 1439 index 46819297fc3e..78b3512d0d63 100644 1440 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h 1441 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h 1442 @@ -363,6 +363,7 @@ 1443 #define ETHSYS_CHIPID4_7 0x4 1444 #define MT7623_ETH 7623 1445 #define MT7622_ETH 7622 1446 +#define MT7621_ETH 7621 1447 1448 /* ethernet subsystem config register */ 1449 #define ETHSYS_SYSCFG0 0x14 1450 @@ -381,6 +382,10 @@ 1451 #define RSTCTRL_FE BIT(6) 1452 #define RSTCTRL_PPE BIT(31) 1453 1454 +/* ethernet RGMII PAD register */ 1455 +#define ETHSYS_RGMII_PAD 0x58 1456 +#define RGMII_PAD_MDIO_DRV_MASK (3 << 4) 1457 + 1458 /* SGMII subsystem config registers */ 1459 /* Register to auto-negotiation restart */ 1460 #define SGMSYS_PCS_CONTROL_1 0x0 1461 @@ -488,6 +493,7 @@ enum mtk_clks_map { 1462 BIT(MTK_CLK_SGMII_CDR_FB) | \ 1463 BIT(MTK_CLK_SGMII_CK) | \ 1464 BIT(MTK_CLK_ETH2PLL)) 1465 +#define MT7621_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW)) 1466 enum mtk_dev_state { 1467 MTK_HW_INIT, 1468 MTK_RESETTING 1469 @@ -567,6 +573,9 @@ struct mtk_rx_ring { 1470 #define MTK_DUAL_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \ 1471 MTK_GMAC2_SGMII) 1472 #define MTK_HWLRO BIT(12) 1473 +#define MTK_SINGLE_IRQ BIT(16) 1474 +#define MTK_RGMII_PAD BIT(17) 1475 +#define MTK_MT7621 (MTK_SINGLE_IRQ | MTK_RGMII_PAD) 1476 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 1477 1478 /* struct mtk_eth_data - This is the structure holding all differences 1479 diff --git a/drivers/staging/mt7621-pinctrl/Kconfig b/drivers/staging/mt7621-pinctrl/Kconfig 1480 index 37cf9c3273be..fc3612711307 100644 1481 --- a/drivers/staging/mt7621-pinctrl/Kconfig 1482 +++ b/drivers/staging/mt7621-pinctrl/Kconfig 1483 @@ -2,3 +2,4 @@ config PINCTRL_RT2880 1484 bool "RT2800 pinctrl driver for RALINK/Mediatek SOCs" 1485 depends on RALINK 1486 select PINMUX 1487 + select GENERIC_PINCONF 1488 diff --git a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 1489 index b8566ed898f1..0bb81c816253 100644 1490 --- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 1491 +++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 1492 @@ -11,6 +11,7 @@ 1493 #include <linux/of.h> 1494 #include <linux/pinctrl/pinctrl.h> 1495 #include <linux/pinctrl/pinconf.h> 1496 +#include <linux/pinctrl/pinconf-generic.h> 1497 #include <linux/pinctrl/pinmux.h> 1498 #include <linux/pinctrl/consumer.h> 1499 #include <linux/pinctrl/machine.h> 1500 @@ -89,6 +90,7 @@ static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev, 1501 ngroups++; 1502 1503 *map = NULL; 1504 + *num_maps = 0; 1505 ret = pinctrl_utils_reserve_map(pctrldev, map, &reserved_maps, 1506 num_maps, ngroups); 1507 if (ret) { 1508 @@ -113,7 +115,8 @@ static const struct pinctrl_ops rt2880_pctrl_ops = { 1509 .get_groups_count = rt2880_get_group_count, 1510 .get_group_name = rt2880_get_group_name, 1511 .get_group_pins = rt2880_get_group_pins, 1512 - .dt_node_to_map = rt2880_pinctrl_dt_node_to_map, 1513 + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1514 +// .dt_node_to_map = rt2880_pinctrl_dt_node_to_map, 1515 .dt_free_map = pinctrl_utils_free_map, 1516 }; 1517 1518 @@ -160,9 +163,9 @@ static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev, 1519 1520 /* dont allow double use */ 1521 if (p->groups[group].enabled) { 1522 - dev_err(p->dev, "%s is already enabled\n", 1523 - p->groups[group].name); 1524 - return -EBUSY; 1525 + dev_info(p->dev, "%s is already enabled\n", 1526 + p->groups[group].name); 1527 + return 0; 1528 } 1529 1530 p->groups[group].enabled = 1; 1531 diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c 1532 index 5c4a764717c4..6482a0d1078c 100644 1533 --- a/drivers/watchdog/mt7621_wdt.c 1534 +++ b/drivers/watchdog/mt7621_wdt.c 1535 @@ -14,6 +14,7 @@ 1536 #include <linux/reset.h> 1537 #include <linux/module.h> 1538 #include <linux/kernel.h> 1539 +#include <linux/of.h> 1540 #include <linux/watchdog.h> 1541 #include <linux/moduleparam.h> 1542 #include <linux/platform_device.h> 1543 diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h 1544 new file mode 100644 1545 index 000000000000..7e6b66a9e644 1546 --- /dev/null 1547 +++ b/include/dt-bindings/clock/mt7621-clk.h 1548 @@ -0,0 +1,37 @@ 1549 +/* 1550 + * Copyright (c) 2017 MediaTek Inc. 1551 + * Author: Chen Zhong <chen.zhong@mediatek.com> 1552 + * 1553 + * This program is free software; you can redistribute it and/or modify 1554 + * it under the terms of the GNU General Public License version 2 as 1555 + * published by the Free Software Foundation. 1556 + * 1557 + * This program is distributed in the hope that it will be useful, 1558 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 1559 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1560 + * GNU General Public License for more details. 1561 + */ 1562 + 1563 +#ifndef _DT_BINDINGS_CLK_MT7621_H 1564 +#define _DT_BINDINGS_CLK_MT7621_H 1565 + 1566 +/* FIXED */ 1567 + 1568 +#define CLK_TOP_XTAL 0 1569 +#define CLK_TOP_ETH_500M 1 1570 +#define CLK_TOP_ETH_SEL 2 1571 +#define CLK_TOP_APLL_SEL 3 1572 +#define CLK_TOP_NR_CLK 4 1573 + 1574 +/* ETHSYS */ 1575 + 1576 +#define CLK_ETHSYS_HSDMA 1 1577 +#define CLK_ETHSYS_ESW 2 1578 +#define CLK_ETHSYS_GDMA 3 1579 +#define CLK_ETHSYS_I2C 4 1580 +#define CLK_ETHSYS_ETH 5 1581 +#define CLK_ETHSYS_CRYPTO 6 1582 +#define CLK_ETHSYS_NR 7 1583 + 1584 +#endif /* _DT_BINDINGS_CLK_MT7621_H */ 1585 + 1586 -- 1587 2.18.1 1588